Designed an 8-Kbit SRAM using sleep transistors to reduce power dissipation. 130nm technology is used to design SRAM cells and HSPICE simulations are used to determine the optimal number and sizes of ...

Undertaking the design of a system-on-a-chip (SoC) is complex enough on its own merits. As is ever more the case, when power consumption is the primary design constraint, it becomes a task of enormous ...

Low-power design is a systemic discipline, so it naturally follows that a design flow intended to address low-power design should also approach the task from a holistic point of view. This has been ...